Memory-Linked Wavefront Array Processor

Reference#: P10194

A method for performing computations with an asynchronous linear array of multiple processing stages is disclosed. The linear array comprises multiple processing stages interspersed with flow control flag mechanisms and with dual port linking memories. The method utilizes the flow control flag mechanisms between processing stages to control the flow of computations through the array. A Memory-Linked Wavefront Array Processor (MWAP) is disclosed which computes a broad range of signal processing and scientific and engineering problems at ultra-high speed. The memory-linked wavefront array processor is an array of identical programmable processing elements linked together by dual-port memory elements that contain a set of special-purpose control flags. All communication in the network is done asynchronously via the linking memory elements, thus providing asynchronous global communication with the processing array. The architecture allows coefficients, intermediate calculations and data used in computations to be stored in the linking elements between processing stages. The novel architecture also allows coefficients, intermediate calculations, and data to be passed between the processing elements in any desired order not restricted by the order data is to be used by the receiving processing element. Further, each processing element is capable of simultaneous arithmetic computation, multi-direction communication, logic discussions, and program control modifications.

Patent Status: U.S. patent(s) 4,922,418 issued. International patents issued.

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