Technologies
Single Event Upset Immune Logic Family
Reference#: P01621
The JHU/APL technology contains a collection of circuits implementing static CMOS logic gates that provide Single Event Upset (SEU) immunity. SEU immunity is obtained by building each logic element with a redundant set of inputs (each input is duplicated), and using two copies of each such logic element to provide redundant outputs.
Patent Status: U.S. patent(s) 6753694; 6756809 issued.
*JHU/APL is seeking a licensee.
CONTACT:Mr. M. T. Hickman
Phone: 443-778-8309
ott-techmanager2@jhuapl.edu
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