Single Event Upset Immune Logic Family

Reference#: P01621

The JHU/APL technology contains a collection of circuits implementing static CMOS logic gates that provide Single Event Upset (SEU) immunity. SEU immunity is obtained by building each logic element with a redundant set of inputs (each input is duplicated), and using two copies of each such logic element to provide redundant outputs.

Patent Status: U.S. patent(s) 6756809; 6753694 issued.

*JHU/APL is seeking a licensee.