Address Sequence Generation by Means of Reverse Carry Addition
An apparatus and method are disclosed for generating a bit reversed sequence. The apparatus includes a reverse addition means for adding binary words in most significant to least significant bit order with the overflow or carry bit propagated to the left. The invention is used to generate a bit reversed address and/or an address sequence that is mapped into a "closed" space.
Patent Status: U.S. patent(s) 4,974,188 issued.CONTACT:
Mr. K. Chao
Phone: (443) 778-7927